The operation of analog circuits relies on continuously changing currents and voltages. The operation of digital circuits relies on the detection of high or low levels at the receiving end based on pre-defined voltage levels or thresholds, which is equivalent to determining the "true" or "false" logic state. There is a "gray" area between the high and low levels of digital circuits, where digital circuits sometimes exhibit analog effects. For example, when jumping from low to high (state), if the speed of the digital signal jumping is fast enough, overshoot and ringing back reflection phenomena will occur.

For modern board design, the concept of mixed signal PCBs is relatively vague because even in pure "digital" devices, analog circuits and effects still exist. Therefore, in the early stages of design, in order to reliably achieve strict timing allocation, simulation effects must be simulated. In fact, in addition to the reliability of communication products that must have fault free continuous operation for several years, simulation effects are particularly needed in low-cost/high-performance consumer products produced in large quantities.

Another challenge in modern mixed signal PCB design is the increasing number of devices with different digital logics, such as GTL LVTTL, LVCMOS, and LVDS logic have different logic thresholds and voltage swing for each type of logic circuit. However, these circuits with different logic thresholds and voltage swing must be designed together on a single PCB. Here, by thoroughly analyzing the layout and wiring design of high-density, high-performance, and mixed signal PCBs, you can master successful strategies and techniques.

1、 Fundamentals of Hybrid Signal Circuit Wiring

When digital and analog circuits share the same components on the same board, the layout and wiring of the circuit must be meticulous. The matrix shown in Figure 1 is helpful for the design and planning of mixed signal PCBs. Only by revealing the characteristics of digital and analog circuits can the required PCB design goals be achieved in actual layout and wiring.

Figure 1: Analog and Digital Circuits: Two aspects of mixed signal design

In mixed signal PCB design, there are special requirements for power supply wiring and isolation between analog noise and digital circuit noise to avoid noise coupling, which increases the complexity of layout and wiring. The special requirements for power transmission lines and the requirement for noise coupling between isolated analog and digital circuits further increase the complexity of the layout and wiring of mixed signal PCBs.

If the power supply of the analog amplifier in the A/D converter is connected together with the digital power supply of the A/D converter, it is likely to cause mutual influence between the analog and digital circuits. Perhaps, due to the placement of input/output connectors, the layout scheme must mix the wiring of digital and analog circuits together.

Before layout and wiring, engineers need to understand the basic weaknesses of the layout and wiring plan. Even with false judgments, most engineers tend to use layout and wiring information to identify potential electrical impacts.

2、 Layout and wiring of modern mixed signal PCBs

The following will explain the technology of mixed signal PCB layout and wiring through the design of the OC48 interface card. OC48 represents the optical carrier standard 48, which is basically aimed at 2.5Gb serial optical communication. It is a high-capacity optical communication standard in modern communication equipment. The OC48 interface card contains several typical layout and wiring issues for mixed signal PCBs, and its layout and wiring process will indicate the order and steps to solve the mixed signal PCB layout scheme.

Figure 2: Logic of OC48 interface card

As shown in Figure 2, The OC48 card includes an optical transceiver that enables bidirectional conversion of optical signals and analog electrical signals. Analog signal input or output digital signal processor, DSP converts these analog signals into digital logic levels, which can be connected to microprocessors, programmable gate arrays, and the system interface circuits of DSP and microprocessors on the OC48 card. The independent phase-locked loop, power filter, and local reference voltage source are also integrated together.

Among them, the microprocessor is a multi power supply device, with a main power supply of 2V and a 3.3V I/O signal power supply shared by other digital devices on the board. The independent digital clock source provides clocks for OC48 I/O, microprocessors, and system I/O.

After checking the layout and wiring requirements of different functional circuit blocks, it is preliminarily recommended to use a 12 layer board, as shown in Figure 3. The configuration of microstrip and stripline layers can safely reduce coupling between adjacent routing layers and improve impedance control. A grounding layer will be set up between the first and second layers to connect sensitive simulation reference sources The wiring of the CPU core and PLL filter power supply is isolated from the microprocessor and DSP devices on the first layer. The power supply and grounding layer always appear in pairs, just like what is done on the OC48 card for sharing the 3.3V power supply layer. This will reduce the impedance between the power supply and ground, thereby reducing noise on the power signal.

Avoid using digital clock lines and high-frequency analog signal lines near the power layer, otherwise the noise of the power signal will be coupled into sensitive analog signals.

According to the needs of digital signal wiring, carefully consider the use of power and analog ground plane openings (splits), especially in the input and output terminals of mixed signal devices. Passing through an open circuit in adjacent signal layers can cause impedance discontinuity and poor transmission line loops. These can all cause signal quality, timing, and EMI issues.

Sometimes by adding several grounding layers or using several peripheral layers for the local power layer or grounding layer under a device, the opening can be cancelled and the above problems can be avoided. Multiple grounding layers are used on the OC48 interface card. Maintaining symmetrical stacking of the opening layer and wiring layer positions can avoid card deformation and simplify the production process. Due to the strong resistance of 1 ounce copper clad plate to high currents, the 3.3V power layer and corresponding grounding layer should use 1 ounce copper clad plate, while other layers can use 0.5 ounce copper clad plate, which can reduce voltage fluctuations caused by transient high currents or peak periods.

If you design a complex system from the ground plane upwards, cards with thicknesses of 0.093 inches and 0.100 inches should be used to support the wiring layer and grounding isolation layer. The thickness of the card must also be adjusted according to the wiring characteristics and dimensions of the through-hole solder pads and holes, so that the aspect ratio of the drilling diameter to the thickness of the finished card does not exceed the aspect ratio of the metalized hole provided by the manufacturer.

If you want to design a low-cost, high-yield commercial product with the minimum number of wiring layers, carefully consider the wiring details of all special power supplies on mixed signal PCBs before layout or wiring. Before starting the layout and wiring, the target manufacturer should review the preliminary layering plan. Basically, layering should be based on the thickness of the finished product, the number of layers, the weight of copper, impedance (with tolerance), and the minimum size of through-hole pads and holes. Manufacturers should provide written layering recommendations.

The suggestion should include configuration examples of all controlled impedance striplines and microstrip lines. Consider combining your prediction of impedance with the manufacturer's prediction of impedance, and then use these impedance predictions to validate the signal wiring characteristics in simulation tools used for developing CAD wiring rules.

3、 Layout of OC48 card

The high-speed analog signal between the optical transceiver and DSP is highly sensitive to external noise. Similarly, all special power and reference voltage circuits also create a significant amount of coupling between the analog and digital power transmission circuits of the card. Sometimes, due to the limitations of the casing shape, high-density boards have to be designed. Due to the orientation of the external fiber optic cable access card and the high size of the optical transceiver components, the position of the transceiver in the card is largely fixed. The position and signal allocation of the system I/O connectors are also fixed. This is the basic work that must be completed before layout (see Figure 4).

Like most successful high-density simulation layouts and wiring schemes, the layout must meet the requirements of wiring, and the requirements of layout and wiring must be balanced. The method of "layout before wiring" is not recommended for the analog part of a mixed signal PCB and the local CPU core with a working voltage of 2V. For OC48 cards, the DSP analog circuit section containing analog reference voltage and analog power supply bypass capacitor should first be interactively wired. After completing the wiring, the entire DSP with analog components and wiring should be placed close enough to the optical transceiver to ensure that the wiring length from the high-speed analog differential signal to the DSP is the shortest, with minimal bending and through holes. The symmetry of differential layout and routing will reduce the impact of common mode noise. However, it is difficult to predict the optimal layout before wiring (see Figure 5).

To consult with chip distributors about the design guidelines for PCB boards. Before designing according to the guidelines, it is necessary to have sufficient communication with the distributor's application engineers. Many chip distributors have strict time limits for providing high-quality fabric recommendations. Sometimes, the solutions they provide are feasible for "first tier customers" who use the device. In the field of signal integrity (SI) design, the signal integrity design of new devices is particularly important. According to the distributor's basic guidelines and combined with specific requirements for each power and ground pin in the packaging, the layout and wiring of the OC48 card integrated with DSP and microprocessor can begin.

After determining the position and wiring of the high-frequency analog part, the remaining digital circuits can be placed according to the grouping method shown in the block diagram. Pay attention to carefully designing the following circuits: the position of the PLL power filter circuit in CPUs with high sensitivity to analog signals; Local CPU core voltage regulator; Reference voltage circuit for "digital" microprocessors.

The electrical and manufacturing standards for digital wiring can only be appropriately applied to the design at this time. The aforementioned design of signal integrity for high-speed digital buses and clock signals reveals some special wiring topology requirements for time delay matching in processor buses, balanced Ts, and certain clock signal wiring. But you may not know, there are also suggestions for updates, such as adding several terminal resistors.

It is natural to make some adjustments during the layout stage during the problem-solving process. However, before starting the wiring, an important step is to verify the timing of the digital part according to the layout plan. At this moment, a complete DFM/DFT layout review of the board will help ensure that the card meets the customer's needs.

4、 Digital wiring of OC48 card

For digital device power lines and the digital part of mixed signal DSPs, the digital wiring should start from the SMD escape patterns. The shortest and widest printed wire allowed by the assembly process should be used. For high-frequency devices, the printed wires of the power supply are equivalent to small inductors, which will worsen power noise and cause unexpected coupling between analog and digital circuits. The longer the power printed line, the greater the inductance.

The optimal layout and wiring scheme can be achieved by using digital bypass capacitors. In short, fine tune the position of the bypass capacitor as needed, making it easy to install and distributed around the digital part of the digital component and mixed signal device. The same "shortest and widest routing" method should be used to wire the bypass capacitor outlet diagram.

When the power branch needs to pass through a continuous plane (such as the 3.3V power layer on the OC48 interface card), the power pins and bypass capacitors themselves do not need to share the same outlet diagram to obtain the lowest inductance and ESR bypass. On mixed signal PCBs like OC48 interface cards, special attention should be paid to the wiring of the power branch. Remember to place additional bypass capacitors in a matrix arrangement throughout the entire card, even near passive components (see Figure 6).

Once the power outlet diagram is determined, automatic wiring can begin. The ATE test contacts on the OC48 card need to be defined during logic design. Ensure that ATE contacts 100% of the nodes. In order to achieve ATE testing with a minimum ATE test probe of 0.070 inches, it is necessary to retain the position of the breakout via to ensure that the power layer is not separated by the cross of the opposing pads of the via.

If a power and ground plane split scheme is to be adopted, a layer bias should be selected on adjacent wiring layers parallel to the opening. Define a prohibited wiring area based on the perimeter of the opening area on adjacent layers to prevent wiring from entering. If the wiring must pass through the open area to another layer, it should be ensured that the adjacent layer to the wiring is a continuous grounding layer. This will reduce the reflection path. Having the bypass capacitor cross the open power layer is beneficial for the layout of some digital signals, but it is not recommended to bridge between the digital and analog power layers because noise can couple with each other through the bypass capacitor.

Several latest automatic wiring applications are capable of wiring high-density multi-layer digital circuits. In the initial wiring stage, 0.050 inch large through-hole spacing should be used in the SMD outlet and the type of packaging used should be considered. In the subsequent wiring stage, the positions of through-holes should be allowed to be relatively close to each other, so that all tools can achieve the highest pass rate and the lowest number of through-holes. Due to the improved star topology adopted by the OC48 processor bus, it has the highest priority during automatic routing (see Figure 7).

Summary

After the completion of the OC48 card board, signal integrity verification and timing simulation should be carried out. The simulation proves that the wiring guidance meets the expected requirements and improves the timing indicators of the second layer bus. The layout task is officially completed when the final design rule inspection, final manufacturing review, mask and review are carried out and signed off to the manufacturer